Abstract
Tesla announced that its AI5 chip has completed tape-out, with Elon Musk highlighting up to 40× performance gains for next-generation FSD and plans for mass production with TSMC and Samsung in late 2026.
On April 15, Elon Musk, CEO of Tesla, announced on X that Tesla’s next-generation AI5 chip has successfully completed tape-out, marking a key milestone in its in-house AI hardware roadmap. He also shared the first official image of the chip.
The AI5 adopts a high-integration design, featuring a large central compute die surrounded by 12 DRAM modules supplied by SK hynix. This layout enables both high memory capacity and optimized bandwidth for data-intensive AI workloads. Chip markings indicate the tape-out occurred in late March 2026.
As the successor to Tesla’s HW4, AI5 is designed to power the company’s next-generation Full Self-Driving (FSD) system. Musk previously stated that it delivers up to 40× overall performance improvement, including 8× higher raw compute and 9× greater memory capacity. A single chip can reach nearly 2,500 TOPS of AI compute with up to 144GB of memory, optimized for Transformer-based models.
AI5 will be available in multiple configurations. A single-SoC version is expected to rival NVIDIA’s Hopper architecture, while a dual-SoC configuration could compete with its newer Blackwell platform. Tesla is also targeting improvements in cost efficiency and performance-per-watt, aiming to challenge existing high-end AI chips.
The chip will be manufactured by TSMC and Samsung, with mass production scheduled for late 2026 to early 2027. Looking ahead, Tesla is advancing future chip programs and its next-generation Dojo supercomputer, as part of a broader push toward vertically integrated AI infrastructure.
