KAIST Develops Ultra-Efficient On-Chip Liquid Cooling Using Manifold Microchannels

Summary:KAIST researchers have developed an on-chip manifold microchannel liquid-cooling system using room-temperature water that achieves ultra-high thermal efficiency and significantly reduces pumping energy for high-performance semiconductor devices.



A research team from KAIST has developed an ultra-efficient liquid-cooling technology that directly dissipates heat inside silicon semiconductor chips, addressing growing thermal constraints in AI and high-performance computing systems.


The system embeds manifold microchannel networks thinner than a human hair directly within the silicon substrate. Unlike conventional single-path microchannel designs, the manifold architecture uses multiple inlets and outlets to distribute coolant more evenly, reducing flow distance, lowering hydraulic resistance, and improving temperature uniformity.


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image: <3D manifold microchannel cooling device for cooling high-power-density semiconductor chips>


Under extreme heat flux conditions exceeding 2,000 W/cm², the chip temperature was maintained below 100°C. The system achieved a coefficient of performance (COP) of 106,000—approximately ten times higher than the previous benchmark of ~10,000 reported in Nature (van Erp et al., 2020)—while reducing pumping power requirements by around 90%.


The design was optimized using a multi-fidelity framework that combined rapid analytical modeling with high-precision simulations to balance channel geometry, flow distribution, and thermal performance. The final structure was fabricated using a semiconductor-compatible process below 350°C, relying solely on room-temperature water without phase-change cooling, nanoscale surface treatments, or expensive materials such as diamond.


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Images for illustration only


This approach offers a scalable thermal management solution for AI accelerators, HPC systems, 3D semiconductor integration, and power electronics. By significantly reducing cooling energy demand at the chip level, it has the potential to alleviate one of the key bottlenecks in data center efficiency and next-generation computing infrastructure.

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